Cypress Semiconductor has just announced the availability of samples of the PSI2G100S, the second in its family of programmable serial interface (PSI) chips

The PSI2G100S integrates a SONET/SDH OC-48 (2.5Gbit/s) transceiver, clock data recovery (CDR) circuitry, a SERDES, 100k gates of programmable logic, and 240Kbit of communications memory, targeting OC-48/STM-12 optical terminators, SONET/SDH routers and add-drop MUX subsystems. The PSI2G100S closely follows the introduction of the PSI2G100, the world's first 2.5Gbit/s programmable PHY.

This article was originally published on Electronicstalk on 23 May 2001 at 8.00am (UK)
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PSI devices offer operating speeds from 1 x 2.5 to 8 x 1.5Gbit/s to support high-bandwidth applications.

PSI devices combine the flexibility, predictable timing, and ease-of-use of Cypress CPLDs with a SERDES, communications memory and phase-locked loops (PLLs).

Cypress's Warp R6.1 software enables a seamless programming interface to allow design engineers to easily integrate custom IP with the serdes via HDL blocks, HDL text, or graphical state machines.
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Cypress is the only company to offer a SONET/SDH OC-48 compliant, 2.5Gbit/s SERDES, programmable logic gates, design entry, synthesis and verification in an integrated, single-chip solution.

"Cypress is delivering the world's first programmable SONET/SDH OC-48 PHY", said Geoff Charubin, director of marketing for Cypress's data communications division.

"The PSI2G100S brings the speed and flexibility of our programmable OC-48 SERDES to SONET/SDH applications, enabling communications solutions designers to develop cutting edge optical solutions and get them to market quickly-and into the OC-48 segment, the sweet spot of the WAN market".

The PSI2G100S is perfectly suited for both port and backplane solutions in a typical line card application.

Its programmability enables customers to create customised and flexible solutions for the parallel-side interface - for example, taking an OC-48 data stream from the serial side and converting it to a 32 or 64bit parallel-bus topology on the other.

The devices in the PSI family provide a programmable interface to a SERDES that is compatible with various physical layer transmission media - fibre-optic modules, copper cables and circuit board traces.

Along with optimised communications memory (such as dual-ported and FIFO memories), logic and PLLs, the ICs will provide parallel programmable I/Os supporting LVCMOS, LVTTL, 3.3V PCI, SSTL2, SSTL3, HSTL, and GTL+ inputs.

The combined serial bandwidth of 200Mbit/s to 12Gbit/s will allow PSI devices to meet the requirements of a broad range of market segments.

The PSI2G100S is the second PSI family product.

Sampling now, the PSI2G100S is available in a 456-ball BGA package.

Volume pricing for the SONET/SDH OC-48, 2.5Gbit/s, 100k-gate, devices is $150.