Actel is sampling the A500K180 and A500K270 flash-based ProASIC 500K gate FPGAs with 369,000 and 473,000 system gates, respectively

Actel is sampling the A500K180 and A500K270 flash-based ProASIC 500K gate FPGAs which, with 369,000 and 473,000 system gates, respectively, are claimed to be the highest-density nonvolatile single-chip "live-at-power-up" reprogrammable solutions available. Implemented in a standard CMOS logic process, the A500K180 and -270 devices combine low power and flash-based nonvolatility with an ASIC-like architecture that delivers predictable performance and great routing efficiency.

This article was originally published on Electronicstalk on 23 April 2001 at 8.00am (UK)
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Specifically, the devices' novel routing hierarchy and structure enable up to 95 percent gate usage, as proven by Actel benchmarks and customer experience.

With this single-chip solution, engineers can use ProASIC devices to create designs that not only meet their system density requirements, but do so using the least amount of components and board real estate.

"Our largest single-chip ProASIC devices are sampling at a time when system designers are looking for ways to improve the efficiency and functionality of their next-generation, high-end designs without the risks and high costs associated with ASICs", said Dennis Kish, vice president, marketing at Actel.

"For the first time, designers can have the best of all worlds - high density, nonvolatility and reprogrammability - in a single device".

The A500K270, the larger of the two devices at 473,000 system gates, offers nearly 27,000 flip flops and 65Kbit of RAM in 28 blocks of 256 x 9bit.
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The 369,000-gate A500K180 offers more than 18,000 flip flops with 55Kbit of RAM in 24 blocks.

As with other members of the ProASIC 500K family, these new devices bring significant benefits to any designer of high-density logic.

For example, ProASIC is single-chip and "live-at-power-up", eliminating the need for a extra boot device such as a serial programmable read only memory (PROM) associated with SRAM FPGAs, thereby simplifying board design and cost.

As a programmable device, the ProASIC family reduces time-to-market and minimises design risk and investment, requiring no mask sets or silicon respins.

Unlike most other PLDs, ProASIC devices operate at very low power, using only one-half the power consumed by SRAM FPGAs and other PLDs based on look-up tables at the same supply voltage.

ProASIC is supported by third-party synthesis, simulation and static timing tools from Exemplar Logic, Model Technology, Synopsys, Synplicity, Cadence and other leading EDA vendors.

The ProASIC software supports major operating systems, including Windows NT, Solaris, HP-UX and SunOS.

The ProASIC place and route design tool was designed from the beginning to support both ASIC and FPGA design flows.

The tool set is based on a complex, multi-million-gate-capable ASIC layout tool that includes timing-driven place and route (TDPR).

The software integrates a global router, static timing analyser, 2.5D-based RC extractor, asymptotic waveform extraction (AWE) delay calculator and an engineering change order (ECO) editor into an advanced design flow.

Additional capabilities include automated memory generation with the ProASIC MemoryMaster tool, power estimation and a layout viewer for identifying and optimising critical paths.

The A500K180 and A500K270 devices are currently available as engineering samples.

Commercial and industrial qualifications for the A500K180 and A500K270 devices are expected in Q3 2001.

Volume pricing for the A500K180 starts at $56.30 and volume pricing for the A500K270 starts at $95.30.