Cypress Semiconductor is sampling the PSI2G100, the first in its family of programmable serial interface (PSI) chips

The PSI2G100 combines a 2.5Gbit/s serial link, 100k gates of programmable logic, and 0.5Mbit of communications memory, and is aimed at system backplanes across a broad range of market segments, including InfiniBand. PSI devices combine the flexibility, predictable timing, and ease-of-use of Cypress CPLDs with a SERDES, communications memory and phase-locked loops (PLLs).

This article was originally published on Electronicstalk on 17 April 2001 at 8.00am (UK)
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Cypress's Warp software enables a seamless programming interface to allow design engineers to easily integrate custom IP with the serdes via HDL blocks, HDL text, or graphical state machines.

Cypress is the only company to offer a 2.5Gbit/s SERDES, programmable logic gates, design entry, synthesis and verification in an integrated, single-chip solution.

"Cypress is delivering a programmable SERDES with all the advantages of our CPLDs: high speed, predictable timing, flexibility, ease of use, and nonvolatility at leadership densities", said Geoff Charubin, director of marketing for Cypress's data communications division.

"The PSI2G100 is precision tuned for custom backplane applications, giving communications solutions designers the ability to interface with their existing processors and ASICs and insert their own custom logic".

"Cypress is first to market with the PSI2G100, ahead of both pure-play data communications/physical-layer companies and programmable-logic specialists", said Ralph Schmitt, Cypress vice president of sales and marketing.
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"Those companies will need to find partners or make acquisitions to achieve the same level of integration and customisation that Cypress can deliver today".

The PSI2G100 has abundant communications memory: 48Kbit of dual-port/FIFO and 192Kbit of single-port RAM for memory-intensive networking functions like queuing, head-of-line blocking and distributed switching.

InfiniBand compliant, the PSI2G100 is a key component in Cypress's PSI family of backplane solutions.

A subset of the family will be SONET-compliant and targeted at the OC-48 market.

The devices in the PSI family provide a programmable interface to a SERDES that is compatible with various physical layer transmission media, fibre-optic modules, copper cables and circuit board traces.

Along with optimised communications memory (such as dual-ported and FIFO memories), logic and PLLs, the ICs will provide multiple parallel I/Os supporting LVCMOS, LVTTL, 3.3V PCI, SSTL2, SSTL3, HSTL, and GTL+ inputs.

The serial links will offer operating speeds from 1 x 2.5 to 8 x 1.5GHz to support high-bandwidth applications.

The combined serial bandwidth of 200Mbit/s to 12Gbit/s will allow PSI devices to meet the requirements of a broad range of market segments.

The PSI2G100 is the first PSI family product.

Sampling now, the PSI2G100 is available in a 456-ball BGA package.

Volume pricing starts at $80.